1. Field of the Invention
The present invention relates to semiconductor devices, and in particular, to a circuit having an adaptive power function.
2. Description of Related Art
FIG. 1 illustrates a prior art data output interface 100 of a semiconductor memory device and a prior art data input interface 200 of a memory controller. As shown, the data output interface 100 includes a data output part 10 that receives data output from a memory cell array (not shown) of the memory device and distributes k bits of parallel data to each of a plurality of parallel-to-serial converters (PSCs) 12-1˜12-n. Each PSC 12 converts the received parallel data to differential serial data do1, do1B˜don, donB.
A clock generator 14 generates k clock signals P1˜Pk to clock the k bits of data for each PSC 12. The clock signals P1˜Pk have different phases from one another, and may be synchronized with an externally received clock signal transferred from the memory controller 200. The PSCs 12 perform the parallel-to-serial conversion operation based on the received clock signals.
The data output interface 100 includes a plurality of output drivers 16-1˜16-n. Each output driver (OD) 16 corresponds to one of the PSCs 12. More specifically, each OD 16 receives the differential serial data, and generates associated differential output signals DO1, DO1B˜Don, DOnB. The differential output signals are sent over a signaling medium such as a bus to the input data interface 200.
A control circuit 18 outputs a control signal CON, which has bits c1˜cm, to the ODs 16. The driving capability of each OD 16 is established in response to the control signal CON. The control circuit 18 includes a fuse structure for setting each bit c1˜cm of the control signal CON. By cutting respective fuses in the fuse structure of the control circuit 18, the fixed value of each bit c1˜cm is set. As will be appreciated, because the control signal CON is fixed, the swing width of the output signals DO1˜DOn and their respective inverses DO1B˜DOnB are also fixed. Stated another way, the driving capability of the ODs 16 is fixed. By setting respective bits in the register structure of the control circuit 18, the value of each bit c1˜cm is set. As will be appreciated, because the control signal CON is set regardless of channel characteristics, the swing width of output signals DO1˜DOn and their respective inverses DO1B˜DOnB are also set regardless of channel characteristics. Stated another way, the driving capability of ODs 16 has no relationship with channel characteristics.
To guarantee stable operation of the memory system including the data output interface 100, the fixed value of the control signal CON, and therefore, the fixed driving capability of the ODs 16 is set relatively high. This also helps ensure high speed operation; but, as will be appreciated is detrimental to reducing power consumption.
As further shown in FIG. 1, the input data interface 200 includes input drivers (ID) 34-1˜34-n, each corresponding to a respective one of the ODs 16. The IDs 34 convert the respectively received differential output data signals to differential input data di1, di1B˜din, dinB. A plurality of serial-to-parallel converters (SPCs) 32-1˜32-n, each convert the differential input data from a respective ID 34 into k bits of parallel data din1˜dinn. A data input part 30 receives the parallel data from the SPCs 32 and outputs an input data stream. As with the output data interface 100, the input data interface 200 includes a clock generator 36. The clock generator 36 generates k clock signals. The clock signals have different phases from one another, and may be synchronized with an internal clock signal of the memory controller 200. The SPCs 32 perform the serial-to-parallel conversion operation based on the received clock signals.